qword

FAULTING_IP: netw5v64+b6d8 fffff880 ` 0aaba6d8 488b4808 mov rcx, qword ptr [rax+8]

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As the name implies, a 64-bit CPU can use a word size 64-bits wide, otherwise known as a quad-word or qword.

Atomic 2009

The compiler for the given function generates these assembler instructions: return FORMULA; fld dword ptr [ebp+8] fadd qword ptr

The Code Project Latest Articles Tomek Kawecki 2009

SIMD (SSE2) optimizations: replaced MOVQ xmm, m64 (rejected by VC9 compiler) with MOVQ xmm, qword ptr m64 and MOVQ m64, xmm with MOVQ qword ptr m64, xmm

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As the name implies, a 64-bit CPU can use a word size 64-bits wide, otherwise known as a quad-word or qword.

Atomic 2009

IoCreateDevice+0×3cc: fffff800 ` 01270bd0 488d4750 lea rax, [rdi+50h] fffff800 ` 01270bd4 48894008 mov qword ptr [rax+8], rax fffff800 ` 01270bd8 488900 mov qword ptr [rax], rax fffff800 ` 01270bdb e95b480000 jmp nt!

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IoCreateDevice+0×3cc: fffff800 ` 01270bd0 488d4750 lea rax, [rdi+50h] fffff800 ` 01270bd4 48894008 mov qword ptr [rax+8], rax fffff800 ` 01270bd8 488900 mov qword ptr [rax], rax fffff800 ` 01270bdb e95b480000 jmp nt!

MSDN Blogs 2008

IoCreateDevice+0×3cc: fffff800 ` 01270bd0 488d4750 lea rax, [rdi+50h] fffff800 ` 01270bd4 48894008 mov qword ptr [rax+8], rax fffff800 ` 01270bd8 488900 mov qword ptr [rax], rax fffff800 ` 01270bdb e95b480000 jmp nt!

MSDN Blogs 2008

IoCreateDevice+0×3cc: fffff800 ` 01270bd0 488d4750 lea rax, [rdi+50h] fffff800 ` 01270bd4 48894008 mov qword ptr [rax+8], rax fffff800 ` 01270bd8 488900 mov qword ptr [rax], rax fffff800 ` 01270bdb e95b480000 jmp nt!

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PspSystemThreadStartup+0×4c fffff800 ` 012b332c 65488b042588010000 mov rax, qword ptr gs: [188h] fffff800 ` 012b3335 483bd8 cmp rbx, rax fffff800 ` 012b3338 0f85a6d30600 jne nt!

MSDN Blogs 2008